1. Field of the Invention
This invention relates to a semiconductor memory device, for example, a semiconductor memory device which is suited for static RAM (random access memory).
2. Description of the Prior Art
Recently, a new memory cell for static RAM comprising one bipolar transistor and one MOS transistor has been announced by Toshiba Corporation at 1988 IEDM (International Electrical Devices Meeting) (for further details, refer to Sakui, K., Hasegawa, T., Fuse, T., Watanabe, S., Ohuchi, K. and Masuoka, F.: "A new static memory cell based on reverse base current (RBC) effect of bipolar transistor", 1988 International Electrical Devices Meeting, Technical Digest, thesis No. 3.2, pp. 44-47, December 1988, or pp. 283-285 of the Nikkei Electronics, 1989. 2. 20 (No. 467)). Aiming at large capacity memory with over 16M bit, this memory cell has a memory principle which is entirely different from that of the conventional static RAM or dynamic RAM in that the two transistors constituting the memory cell, a P-channel MIOS transistor and an NPN transistor, respectively, are used as a transistor for selecting and a transistor for memorizing. And the output of said memory cell shows a high level when the base-emitter voltage of said NPN transistor is about 0.9 V, and a low level when said voltage is 0 V (that is, the NPN transistor takes bistable states), and these two states, respectively, are equivalent to "1" or "0".
The operating principle of said memory cell and its problems will be described hereunder with reference to FIGS. 12 and 13.
The operating principle of this memory cell is to utilize a physical phenomenon, called impact ionization, of the NPN transistor: as shown in FIG. 12, when a collector-emitter voltage V.sub.CE of about 6 V is applied to the NPN transistor which has an emitter-collector dielectric breakdown voltage of about 13 V, electron-hole pairs by impact ionization are generated at a base-collector PN junction region by electrons injected from the emitter at this time. Out of the electron-hole pairs, the electrons move to the collector, and the holes to the base, and an ordinary forward hole current I.sub.BF, which flows from a base to the emitter, is restricted by a base-emitter voltage V.sub.BE, so that the holes generated by impact ionization flow as a reverse hole current (hereinafter may be called simply reverse base current) I.sub.BR in a direction reverse to the ordinary hole current I.sub.BF.
Furthermore, the base current I.sub.B when impact ionization is going on may be expressed as follows: ##EQU1## wherein I.sub.C is a collector current, and M is an impact ionization coefficient. M is expressed by the following formula: EQU M=1/[1-(V.sub.BC /BV.sub.CBO).sup.n ]
wherein V.sub.BC is a voltage applied between the base, and the collector, and BV.sub.CBO is an insulation breakdown voltage of the base-collector PN junction. In this case the test results and the actual calculations are considered to agree when n is assumed as 4.6.
In a cell actually produced for trial, as shown in FIG. 13, when 0.57 V&lt;V.sub.BE &lt;0.90 V, the reverse hole current I.sub.BR becomes greater than the forward hole current I.sub.BR, and when the base-emitter voltage V.sub.BE is set at around 0.9 V, both the reverse and forward currents become equal, leading the base current I.sub.B to stop apparently. Even though the P-channel MOS transistor for selecting is closed in such a state, V.sub.BE remains at about 0.9 V, and this state is "1". In addition, when V.sub.BE is set at 0 V, the base current I.sub.B does not flow, presenting a state of "0".
In practice, when the P-channel MOS transistor is closed with V.sub.BE set at 0.5 V or higher, the hole current stops, leading to V.sub.BE of about 0.9 V, so that it is not necessary to set it at 0.9 V from the outset. Furthermore, when V.sub.BE is smaller than 0.5 V, it likewise becomes 0 V.
As described above, the operating principle of the foregoing memory cell lies in impact ionization in the NPN transistor, wherein a memory operation is performed by finding a logical state of memory in the base-emitter voltage V.sub.BE when the base current I.sub.B becomes 0 through utilization of the positive-negative inversion of said base current I.sub.B caused by the outflow of holes (the reverse hole current I.sub.BR) from a base electrode, said holes being those of the electron-hole pairs generated by impact ionization at the collector-base PN-junction region.
Said base current I.sub.B, as shown in FIG. 13, changes in the order of "+", "-" and "+" accompanied by the change of the base-emitter voltage V.sub.BE, and the range of the base-emitter voltage during the flow of negative current is 0.57 V&lt;V.sub.BE &lt;0.90 V. However, when the device is used within the above-mentioned voltage range in an ordinary bipolar transistor, though depending upon the shape of transistor, a relatively large collector current I.sub.C inevitably flows. This causes a very big problem in producing a large capacity static RAM as described above.
Actually in the memory cell announced by Toshiba Corp. it has been confirmed that said memory cell induces the flow of a collector current such as 500 uA per bipolar transistor for memorizing. Hence this leads to a very high consumption of power in consideration of a large capacity static RAM in practice.
Incidentally, FIG. 14 shows the V.sub.BE -I.sub.B and I.sub.C characteristic of said NPN transistor based on the so-called Gummel plot when the collector-emitter voltage V.sub.CE is set at 6.25 V.